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| MTC20455 QUAD ADSL DMT TRANSCEIVER Quad DMT modem ATM framer Supports ANSI T1.413 issue 2, ITU G.992.1, and G.992.2 standards Low power consumption (1W for four lines) Standard Utopia level 2 ATM interface 160 PQFP Package 160 LFBGA Package PQFP160 LFBGA160 ORDERING NUMBERS: Part Numbers MTC20455PQ-I MTC20455MB-I Package 160 pin PQFP 160 pin LFBGA Temperature -40 to +85C -40 to +85C DESCRIPTION The MTC20455 is the DMT modem and ATM Framer of the MTK20450 Quad Rate adaptive ADSL DynaMiTe chipset. When used in conjunction with the MTC20454 or MTC20154 analog front-end, the product supports ANSI T1.413 release 2, ITU G.992.1 and G.992.2 (G.Lite) ADSL specifications through software configuration. It provides a cell based UTOPIA Level 2 ATM data interface. The MTC20455 performs the DMT modulation, demodulation, Reed-Solomon encoding, bit interleaving and trellis coding for four ADSL modems. The ATM section provides framing functions for Figure 1. Block Diagram AFE Can also be ordered using kit number MTK20450 the generic and ATM Transmission Convergence (TC) layers. The generic TC consists of data scrambling and Reed-Solomon error corrections, with and without interleaving. The MTC20455 is controlled and configured by the MTC20136 Transceiver Controller. All programmable coefficients and parameters are loaded by the Controller. The MTC20136 also controls the initialisation procedure and performs the monitoring and adaptive functions during operation. Quad or Mux'd AFE Interface Reset DynaMiTe Core 0 DynaMiTe Core 1 Transceiver Controller Test DynaMiTe Core 2 DynaMiTe Core 3 JTAG Clocks Interface Module UTOPIA Interface February 2004 1/23 MTC20455 Figure 2. PQF160 package pin out VDD U_TXREFB U_TXDATA_7 U_TXDATA_6 U_TXDATA_5 U_TXDATA_4 U_TXDATA_3 U_TXDATA_2 U_TXDATA_1 U_TXDATA_0 VSS COMP_CELL VDD U_TXADDR_4 U_TXADDR_3 U_TXADDR_2 U_TXADDR_1 U_TXADDR_0 VSS U_TXCLAV U_TXENBB U_TXCLK VDDIO U_TXSOC AFTXD_3_3 AFTXD_3_2 AFTXD_3_1 AFTXD_3_0 VSSIO CTRLDATA_3 MCLK_3 CLWD_3 VDD AFRXD_3_3 AFRXD_3_2 AFRXD_3_1 AFRXD_3_0 PDOWN_3 AFRESET_3 VSS AD_00 AD_01 AD_02 AD_03 VDDIO AD_04 AD_05 AD_06 AD_07 VSSIO AD_08 AD_09 AD_10 AD_11 VDD AD_12 AD_13 AD_14 AD_15 VSS PCLK BE ALE CSB_0 VDD CSB_1 CSB_2 CSB_3 WR_RDB VSS RDYB OBC_TYPE INTB_0 INTB_1 VDD INTB_2 INTB_3 RESETB VSS 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 099 098 097 096 095 094 093 092 091 090 089 088 087 086 085 084 083 082 081 VSS UTOPIA TX AFE_0 OBC MTC20455 (PQFP160) AFE_2 VDD AFTXD_2_3 AFTXD_2_2 AFTXD_2_1 AFTXD_2_0 VSS CTRLDATA_2 MCLK_2 CLWD_2 VDD AFRXD_2_3 AFRXD_2_2 AFRXD_2_1 AFRXD_2_0 VDDIO PDOWN_2 AFRESET_2 GP_IN VSS AFTXD_1_3 AFTXD_1_2 AFTXD_1_1 AFTXD_1_0 VSSIO CTRLDATA_1 MCLK_1 CLWD_1 VDD AFRXD_1_3 AFRXD_1_2 AFRXD_1_1 AFRXD_1_0 PDOWN_1 AFRESET_1 VDDIO AFTXD_0_3 AFTXD_0_2 AFTXD_0_1 AFTXD_0_0 VSS TEST UTOPIA RX AFE_3 Table 1. I/O types Type I I-PD I-PU O OZ B G P Function Input Input with internal pull down resistor Input with internal pull up resistor Output Tri-state output Bidirectional Ground Power 2/23 VDD TDO TDI TMS TCK TRSTB VSS TESTSE VSSIO U_RXDATA_0 U_RXDATA_1 U_RXDATA_2 U_RXDATA_3 U_RXDATA_4 U_RXDATA_5 U_RXDATA_6 U_RXDATA_7 VDDIO U_RXSOC U_RXCLK U_RXENBB U_RXCLAV VDD URXADDR_0 URXADDR_1 URXADDR _2 URXADDR_3 URXADDR_4 VSS AFRESET_0 PDOWN_0 AFRXD_0_0 AFRXD_0_1 AFRXD_0_2 AFRXD_0_3 VSSIO CLWD_0 MCLK_0 CTRLDATA_0 VDD 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 AFE_1 MTC20455 Table 2. I/O driver function Driver BD4STARP_TC BD8STARP_TC TLCHT_TC TLCHTDQ_TC TLCHTUQ_TC Function CMOS bi-directional, 4mA, schmitt trigger on input, active slew rate control, 3.3V capable CMOS bi-directional, 8mA, schmitt trigger on input, active slew rate control, 3.3V capable TTL input, 3.3V compatible TTL input, 3.3V compatible, pull down, IDDq control TTL input, 3.3V compatible, pull up, IDDq control Table 3. PQFP 160 pin list Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Signal Name VSS AD_00 AD_01 AD_02 AD_03 VDDIO AD_04 AD_05 AD_06 AD_07 VSSIO AD_08 AD_09 AD_10 AD_11 VDD AD_12 AD_13 AD_14 AD_15 VSS PCLK BE ALE CSB_0 VDD CSB_1 CSB_2 CSB_3 WR_RDB VSS RDYB OBC_TYPE INTB_0 Signal type G B B B B P B B B B G B B B B P B B B B G I I I I P I I I I G OZ I-PD O BD4STARP_TC TLCHTDQ_TC BD4STARP_TC Ready indication I960/Generic selection Requests OBC interrupt service line 0 TLCHT_TC TLCHT_TC TLCHT_TC TLCHT_TC TLCHT_TC TLCHT_TC TLCHT_TC TLCHT_TC Processor Clock Address bit 1 Address Latch Chip select line 0 VSS+1.8V Chip select line 1 Chip select line 2 Chip select line 3 Write/Not read BD8STARP_TC BD8STARP_TC BD8STARP_TC BD8STARP_TC BD8STARP_TC BD8STARP_TC BD8STARP_TC BD8STARP_TC Address/Data Bus Address/Data Bus Address/Data Bus Address/Data Bus VSS+1.8V Address/Data Bus Address/Data Bus Address/Data Bus Address/Data Bus BD8STARP_TC BD8STARP_TC BD8STARP_TC BD8STARP_TC BD8STARP_TC BD8STARP_TC BD8STARP_TC BD8STARP_TC Address/Data Bus Address/Data Bus Address/Data Bus Address/Data Bus VSSIO+3.3V Address/Data Bus Address/Data Bus Address/Data Bus Address/Data Bus Technology Description 3/23 MTC20455 Table 3. PQFP 160 pin list (continued) Pin # 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 Signal Name INTB_1 VDD INTB_2 INTB_3 RESETB VSS VDD TDO TDI TMS TCK TRSTB VSS TESTE VSSIO U_RXDATA_0 U_RXDATA_1 U_RXDATA_2 U_RXDATA_3 U_RXDATA_4 U_RXDATA_5 U_RXDATA_6 U_RXDATA_7 VDDIO U_RXSOC U_RXCLK U_RXENBB U_RXCLAV VDD U_RXADDR_0 U_RXADDR_1 U_RXADDR_2 U_RXADDR_3 U_RXADDR_4 VSS AFRESET_0 PDOWN_0 AFRXD_0_0 AFRXD_0_1 AFRXD_0_2 AFRXD_0_3 VSSIO CLWD_0 Signal type O P O O I G P OZ I-PU I-PU I-PD I-PD G I-PD G OZ OZ OZ OZ OZ OZ OZ OZ P OZ I I OZ P I I I I I G O O I I I I G I TLCHT_TC Start of word indication line 0 BD4STARP_TC BD4STARP_TC TLCHT_TC TLCHT_TC TLCHT_TC TLCHT_TC MTC20455 Reset line 0 MTC20455 power down line 0 Receive data nibble line 0 Receive data nibble line 0 Receive data nibble line 0 Receive data nibble line 0 TLCHT_TC TLCHT_TC TLCHT_TC TLCHT_TC TLCHT_TC BD8STARP_TC TLCHT_TC TLCHT_TC BD8STARP_TC BD8STARP_TC BD8STARP_TC BD8STARP_TC BD8STARP_TC BD8STARP_TC BD8STARP_TC BD8STARP_TC Utopia receive data bus Utopia receive data bus Utopia receive data bus Utopia receive data bus Utopia receive data bus Utopia receive data bus Utopia receive data bus Utopia receive data bus VSSIO+3.3V Utopia receive start of cell Utopia receive clock Utopia receive not enable Utopia receive cell available VSS+1.8V Utopia receive address Utopia receive address Utopia receive address Utopia receive address Utopia receive address TLCHTDQ_TC Enables scan test mode BD4STARP_TC TLCHTUQ_TC TLCHTUQ_TC TLCHTDQ_TC TLCHTDQ_TC VSS+1.8V Boundary scan out Boundary scan in Tap controller signal Boundary scan clock Not reset of Tap controller BD4STARP_TC BD4STARP_TC TLCHT_TC Technology BD4STARP_TC Description Requests OBC interrupt service line 1 VSS+1.8V Requests OBC interrupt service line 2 Requests OBC interrupt service line 3 Hard reset 4/23 MTC20455 Table 3. PQFP 160 pin list (continued) Pin # 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Signal Name MCLK_0 CTRLDATA_0 VDD VSS AFTXD_0_0 AFTXD_0_1 AFTXD_0_2 AFTXD_0_3 VDDIO AFRESET_1 PDOWN_1 AFRXD_1_0 AFRXD_1_1 AFRXD_1_2 AFRXD_1_3 VDD CLWD_1 MCLK_1 CTRLDATA_1 VSSIO AFTXD_1_0 AFTXD_1_1 AFTXD_1_2 AFTXD_1_3 VSS GP_IN AFRESET_2 PDOWN_2 VDDIO AFRXD_2_0 AFRXD_2_1 AFRXD_2_2 AFRXD_2_3 VDD CLWD_2 MCLK_2 CTRLDATA_2 VSS AFTXD_2_0 AFTXD_2_1 AFTXD_2_2 AFTXD_2_3 VDD Signal type I O P G O O O O P O O I I I I P I I O G O O O O G I-PD O O P I I I I P I I O G O O O O P BD4STARP_TC BD4STARP_TC BD4STARP_TC BD4STARP_TC Transmit data nibble line 2 Transmit data nibble line 2 Transmit data nibble line 2 Transmit data nibble line 2 VSS+1.8V TLCHT_TC TLCHT_TC BD4STARP_TC TLCHT_TC TLCHT_TC TLCHT_TC TLCHT_TC TLCHTDQ_TC BD4STARP_TC BD4STARP_TC General purpose input for DspFe test MTC20455 Reset line 2 MTC20455 power down line 2 VSSIO+3.3V Receive data nibble line 2 Receive data nibble line 2 Receive data nibble line 2 Receive data nibble line 2 VSS+1.8V Start of word indication line 2 Master clock line 2 Serial data transmit channel line 2 BD4STARP_TC BD4STARP_TC BD4STARP_TC BD4STARP_TC Transmit data nibble line 1 Transmit data nibble line 1 Transmit data nibble line 1 Transmit data nibble line 1 TLCHT_TC TLCHT_TC BD4STARP_TC BD4STARP_TC BD4STARP_TC TLCHT_TC TLCHT_TC TLCHT_TC TLCHT_TC BD4STARP_TC BD4STARP_TC BD4STARP_TC BD4STARP_TC Transmit data nibble line 0 Transmit data nibble line 0 Transmit data nibble line 0 Transmit data nibble line 0 VSSIO+3.3V MTC20455 Reset line 1 MTC20455 power down line 1 Receive data nibble line 1 Receive data nibble line 1 Receive data nibble line 1 Receive data nibble line 1 VSS+1.8V Start of word indication line 1 Master clock line 1 Serial data transmit channel line 1 Technology TLCHT_TC BD4STARP_TC Description Master clock line 0 Serial data transmit channel line 0 VSS+1.8V 5/23 MTC20455 Table 3. PQFP 160 pin list (continued) Pin # 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Signal Name VSS AFRESET_3 PDOWN_3 AFRXD_3_0 AFRXD_3_1 AFRXD_3_2 AFRXD_3_3 VDD CLWD_3 MCLK_3 CTRLDATA_3 VSSIO AFTXD_3_0 AFTXD_3_1 AFTXD_3_2 AFTXD_3_3 U_TXSOC VDDIO U-TXCLK U_TXENBB U_TXCLAV VSS U_TXADDR_0 U_TXADDR_1 U_TXADDR_2 U_TXADDR_3 U_TXADDR_4 VDD COMP_CELL VSS U_TXDATA_0 U_TXDATA_1 U_TXDATA_2 U_TXDATA_3 U_TXDATA_4 U_TXDATA_5 U_TXDATA_6 U-TXDATA_7 U_TXREFB VDD Signal type G O O I I I I P I I O G O O O O I P I I OZ G I I I I I P O G I I I I I I I I I P TLCHT_TC TLCHT_TC TLCHT_TC TLCHT_TC TLCHT_TC TLCHT_TC TLCHT_TC TLCHT_TC TLCHT_TC Utopia transmit data bus Utopia transmit data bus Utopia transmit data bus Utopia transmit data bus Utopia transmit data bus Utopia transmit data bus Utopia transmit data bus Utopia transmit data bus 8kHz from network VSS+1.8V COMPENSATION_VSS TLCHT_TC TLCHT_TC TLCHT_TC TLCHT_TC TLCHT_TC Utopia transmit address Utopia transmit address Utopia transmit address Utopia transmit address Utopia transmit address VSS+1.8V Resistance for compensation cell TLCHT_TC TLCHT_TC BD8STARP_TC BD4STARP_TC BD4STARP_TC BD4STARP_TC BD4STARP_TC TLCHT_TC Transmit data nibble line 3 Transmit data nibble line 3 Transmit data nibble line 3 Transmit data nibble line 3 Utopia transmit start of cell VSSIO+3.3V Utopia transmit clock Utopia transmit not enable Utopia transmit cell available TLCHT_TC TLCHT_TC BD4STARP_TC BD4STARP_TC BD4STARP_TC TLCHT_TC TLCHT_TC TLCHT_TC TLCHT_TC MTC20455 Reset line 3 MTC20455 power down line 3 Receive data nibble line 3 Receive data nibble line 3 Receive data nibble line 3 Receive data nibble line 3 VSS+1.8V Start of word indication line 3 Master clock line 3 Serial data transmit channel line 3 Technology Description 6/23 MTC20455 Figure 3. LFBGA160 package pin out (Sachem4 top view) 1 AD_0 2 VDD_7 3 4 5 VDD_5 6 U_TXADDR_1 7 U_TXCLAV 8 U_TXSOC 9 AFTXD_3_1 10 MCLK_3 11 AFRXD_3_3 12 AFRXD_3_0 13 VSS_2 14 AFRESET_3 U_TXDATA_4 U_TXDATA_0 A B C D E F G H J K L M N P VSS_7 U_TXREFB U_TXDATA_7 U_TXDATA_5 U_TXDATA_2 COMP_CELL U_TXADDR_2 U_TXENBB VDDIO_4 AFTXD_3_0 CLWD_3 PDOWN_3 AFTXD_2_3 VDD_2 VDDIO_8 AD_2 AD_1 U_TXDATA_6 U_TXDATA_3 VSS_6 U_TXADDR_3 VSS_4 AFTXD_3_3 VSS_3 VDD_3 AFRXD_3_2 AFTXD_2_2 VSS_1 AD_7 AD_3 AD_5 AD_4 U_TXDATA_1 U_TXADDR_4 U_TXADDR_0 U_TXCLK AFTXD_3_2 CTRLDATA_3 AFTXD_2_0 AFRXD_3_1 AFTXD_2_1 VDD_1 AD_10 AD_6 AD_11 VSS_8 open open open open open open MCLK_2 CTRLDATA_2 CLWD_2 AFRXD_2_1 AD_12 AD_9 AD_8 VDD_9 open open open open open open AFRXD_2_0 AFRXD_2_3 AFRXD_2_2 AFRESET_2 VSS_9 AD_13 AD_14 AD_15 open open open open open open GP_IN VDDIO_0 PDOWN_2 AFTXD_1_2 ALE PCLK BE VDD_10 open open open open open open AFTXD_1_1 VSS_0 AFTXD_1_3 VSS_17 CSB_2 CSB_0 CSB_1 WR_RDB open open open open open open MCLK_1 CTRLDATA_1 AFTXD_1_0 CLWD_1 RDYB CSB_3 VSS_10 VDD_11 open open open open open open AFRXD_1_2 AFRXD_1_3 VDD_17 AFRXD_1_1 INTB_1 OBC_TYPE INTB_0 TCK U_RXDATA_0 U_RXDATA_4 VDDIO_13 U_RXCLAV U_RXADDR_2AFRESET_0 PDOWN_1 AFRESET_1 AFRXD_1_0 VDDIO_16 INTB_3 INTB_2 TDI VSS_12 U_RXDATA_1 U_RXDATA_5 U_RXSOC U_RXADDR_1 VSS_14 AFRXD_0_2 AFRXD_0_0 AFTXD_0_2 AFTXD_0_3 AFTXD_0_1 VSS_11 RESETB TMS TESTSE U_RXDATA_2 U_RXDATA_6 U_RXCLK VDD_14 U_RXADDR_4AFRXD_0_1 VSS_15 MCLK_0 AFTXD_0_0 VSS_16 VDD_12 TDO TRSTB VSS_13 U_RXDATA_3 U_RXDATA_7 U_RXENBB U_RXADDR_0 U_RXADDR_3 PDOWN_0 AFRXD_0_3 CLWD_0 VDD_15 CTRLDATA_0 Table 4. LFBGA 160 pin list Pin # B1 A1 C3 C2 D2 C1 D4 D3 E2 D1 E4 F3 F2 E1 E3 Signal Name VSS AD_00 AD_01 AD_02 AD_03 VDDIO AD_04 AD_05 AD_06 AD_07 VSSIO AD_08 AD_09 AD_10 AD_11 Signal type G B B B B P B B B B G B B B B BD8STARP_TC BD8STARP_TC BD8STARP_TC BD8STARP_TC Address/Data Bus Address/Data Bus Address/Data Bus Address/Data Bus BD8STARP_TC BD8STARP_TC BD8STARP_TC BD8STARP_TC BD8STARP_TC BD8STARP_TC BD8STARP_TC BD8STARP_TC Address/Data Bus Address/Data Bus Address/Data Bus Address/Data Bus VSSIO+3.3V Address/Data Bus Address/Data Bus Address/Data Bus Address/Data Bus Technology Description 7/23 MTC20455 Table 4. LFBGA 160 pin list (continued) Pin # F4 F1 G2 G3 G4 G1 H2 H3 H1 J2 H4 J3 J1 K2 J4 K3 K1 L2 L3 L1 K4 M2 M1 N2 N1 P1 P2 M3 N3 L4 P3 M4 N4 P4 L5 M5 N5 P5 L6 M6 N6 P6 L7 Signal Name VDD AD_12 AD_13 AD_14 AD_15 VSS PCLK BE ALE CSB_0 VDD CSB_1 CSB_2 CSB_3 WR_RDB VSS RDYB OBC_TYPE INTB_0 INTB_1 VDD INTB_2 INTB_3 RESETB VSS VDD TDO TDI TMS TCK TRSTB VSS TESTE VSSIO U_RXDATA_0 U_RXDATA_1 U_RXDATA_2 U_RXDATA_3 U_RXDATA_4 U_RXDATA_5 U_RXDATA_6 U_RXDATA_7 VDDIO Signal type P B B B B G I I I I P I I I I G OZ I-PD O O P O O I G P OZ I-PU I-PU I-PD I-PD G I-PD G OZ OZ OZ OZ OZ OZ OZ OZ P BD8STARP_TC BD8STARP_TC BD8STARP_TC BD8STARP_TC BD8STARP_TC BD8STARP_TC BD8STARP_TC BD8STARP_TC Utopia receive data bus Utopia receive data bus Utopia receive data bus Utopia receive data bus Utopia receive data bus Utopia receive data bus Utopia receive data bus Utopia receive data bus VSSIO+3.3V TLCHTDQ_TC Enables scan test mode BD4STARP_TC TLCHTUQ_TC TLCHTUQ_TC TLCHTDQ_TC TLCHTDQ_TC VSS+1.8V Boundary scan out Boundary scan in Tap controller signal Boundary scan clock Not reset of Tap controller BD4STARP_TC BD4STARP_TC TLCHT_TC BD4STARP_TC TLCHTDQ_TC BD4STARP_TC BD4STARP_TC Ready indication I960/Generic selection Requests OBC interrupt service line 0 Requests OBC interrupt service line 1 VSS+1.8V Requests OBC interrupt service line 2 Requests OBC interrupt service line 3 Hard reset TLCHT_TC TLCHT_TC TLCHT_TC TLCHT_TC TLCHT_TC TLCHT_TC TLCHT_TC TLCHT_TC Processor Clock Address bit 1 Address Latch Chip select line 0 VSS+1.8V Chip select line 1 Chip select line 2 Chip select line 3 Write/Not read BD8STARP_TC BD8STARP_TC BD8STARP_TC BD8STARP_TC Technology VSS+1.8V Address/Data Bus Address/Data Bus Address/Data Bus Address/Data Bus Description 8/23 MTC20455 Table 4. LFBGA 160 pin list (continued) Pin # M7 N7 P7 L8 N8 D11 D13 C13 B13 B14 A13 A14 B12 A12 D12 C12 A11 C11 B11 A10 D10 C10 B10 A9 D9 C9 A8 B9 D8 B8 A7 C8 D7 A6 B7 C7 D6 A5 B6 C6 A4 D5 B5 Signal Name U_RXSOC U_RXCLK U_RXENBB U_RXCLAV VDD AFTXD_2_0 AFTXD_2_1 AFTXD_2_2 AFTXD_2_3 VDD VSS AFRESET_3 PDOWN_3 AFRXD_3_0 AFRXD_3_1 AFRXD_3_2 AFRXD_3_3 VDD CLWD_3 MCLK_3 CTRLDATA_3 VSSIO AFTXD_3_0 AFTXD_3_1 AFTXD_3_2 AFTXD_3_3 U_TXSOC VDDIO U-TXCLK U_TXENBB U_TXCLAV VSS U_TXADDR_0 U_TXADDR_1 U_TXADDR_2 U_TXADDR_3 U_TXADDR_4 VDD COMP_CELL VSS U_TXDATA_0 U_TXDATA_1 U_TXDATA_2 Signal type OZ I I OZ P O O O O P G O O I I I I P I I O G O O O O I P I I OZ G I I I I I P O G I I I TLCHT_TC TLCHT_TC TLCHT_TC Utopia transmit data bus Utopia transmit data bus Utopia transmit data bus COMPENSATION_VSS TLCHT_TC TLCHT_TC TLCHT_TC TLCHT_TC TLCHT_TC Utopia transmit address Utopia transmit address Utopia transmit address Utopia transmit address Utopia transmit address VSS+1.8V Resistance for compensation cell TLCHT_TC TLCHT_TC BD8STARP_TC BD4STARP_TC BD4STARP_TC BD4STARP_TC BD4STARP_TC TLCHT_TC Transmit data nibble line 3 Transmit data nibble line 3 Transmit data nibble line 3 Transmit data nibble line 3 Utopia transmit start of cell VSSIO+3.3V Utopia transmit clock Utopia transmit not enable Utopia transmit cell available TLCHT_TC TLCHT_TC BD4STARP_TC BD4STARP_TC BD4STARP_TC TLCHT_TC TLCHT_TC TLCHT_TC TLCHT_TC MTC20455 Reset line 3 MTC20455 power down line 3 Receive data nibble line 3 Receive data nibble line 3 Receive data nibble line 3 Receive data nibble line 3 VSS+1.8V Start of word indication line 3 Master clock line 3 Serial data transmit channel line 3 BD4STARP_TC BD4STARP_TC BD4STARP_TC BD4STARP_TC Technology BD8STARP_TC TLCHT_TC TLCHT_TC Description Utopia receive start of cell Utopia receive clock Utopia receive not enable Utopia receive cell available VSS+1.8V Transmit data nibble line 2 Transmit data nibble line 2 Transmit data nibble line 2 Transmit data nibble line 2 VSS+1.8V 9/23 MTC20455 Table 4. LFBGA 160 pin list (continued) Pin # C5 A3 B4 C4 B3 B2 A2 Signal Name U_TXDATA_3 U_TXDATA_4 U_TXDATA_5 U_TXDATA_6 U-TXDATA_7 U_TXREFB VDD Signal type I I I I I I P Technology TLCHT_TC TLCHT_TC TLCHT_TC TLCHT_TC TLCHT_TC TLCHT_TC Description Utopia transmit data bus Utopia transmit data bus Utopia transmit data bus Utopia transmit data bus Utopia transmit data bus 8kHz from network VSS+1.8V ELECTRICAL SPECIFICATIONS GENERIC The values presented in the following table apply for all inputs and/or outputs unless specified otherwise. Specifically they are not influenced by the choice between CMOS or TTL levels. Table 5. I/O Buffers generic DC Characteristics DC Electrical Characteristics All voltages are referenced to Vss, unless otherwise specified, positive current is towards the device Symbol IIN IOZ IPU IPD Rpu RPD IDC Parameter Input leakage current Tristate leakage current Pull up current Pull down current Pull up resistance Pull down resistance Static current fromVDDIO Test Conditions VIN = VSS, VDDIO, no pull up/pull down VIN = VSS, VDDIO, no pull up/pull down VIN = VSS VIN = VDDIO VIN = VSS VIN = VDDIO NORMAL MODE COREOFF MODE (no VDD) IDDQ MODE (VDDIO <2.5) -15 12.5 35 40 1.7 11.6 -46.7 39.4 70.5 83.7 -100 90 200 240 A A kOhm kOhm A A A Min -1 -1 Typ Max 1 1 Unit A A Table 6. IO buffers dynamic characteristic DC Electrical Characteristics, important for transient but measured at (near) DC. All voltages are referenced to VSS, unless otherwise specified, positive current is towards the device Symbol CIN dl/dt Ipeak COUT Parameter Input capacitance Current derivative Peak current Output capacitance (also bidirectional and tristate drivers) Test Conditions @f = 1 MHz 8 mA driver, (active slew rate control) 8 mA driver, (active slew rate control) @f = 1MHz 20 85 7 Min Typ Max 5 50 Unit pF mA/ns mA pF 10/23 MTC20455 Input/Output CMOS Generic Characteristics The values presented in the following table apply for all CMOS inputs and/ or outputs unless specified otherwise. Table 7. TTL IO buffers generic characteristics DC Electrical Characteristics All voltages are referenced to VSS, unless otherwise specified, positive current is towards the device Symbol VIL VIH VHY VOL VOH Parameter Low level input voltage High level input voltage Schmitt trigger hysteresis Low level output voltage High level output voltage slow edge <1V/s only for SCHMITT IOUT = XMa* IOUT = -Xma* 0.85*vDD 0.8*vDD 0.8 0.4 Test Conditions Min Typ Max 0.2*VDD Unit V V V V V * The reference current is dependent on the exact buffer chosen and is part of the buffer name. The available values are 4 and 8mA. Input/Output TTL Generic Characteristics The values presented in the following table apply for all TTL inputs and/or outputs unless specified otherwise. Table 8. TTL IO buffers generic characteristics DC Electrical Characteristics, important for transient but measured at (near) DC. All voltages are referenced to VSS, unless otherwise specified, positive current is towards the device Symbol VIL VIH VILHY VIHHY VHY VOL VOH Parameter Low level input voltage High level input voltage Low level threshold, falling slow edge < 1V/s High level threshold, rising Schmitt trigger hysteresis Low level output voltage High level output voltage slow edge < 1V/s slow edge <1V/s IOUT = XMa* IOUT = -Xma* 2.4 2.0 0.9 1.3 0.4 1.35 1.9 0.7 0.4 Test Conditions Min Typ Max 0.8 Unit V V V V V V V * The reference current is dependent on the exact buffer chosen and is part of the buffer name. The available values are 2,4, and 8mA. Operating Conditions Table 9. Operating Conditions Maximum ratings Symbol VDDIO VDD TA P Parameter IO Supply voltage Core Supply voltage Ambient temperature 1m/s airflow Power dissipation Test Conditions Min 3.0 1.62 -40 Typ 3.3 1.8 Max 3.6 2.0 +85 1000 Unit V V C mW 11/23 MTC20455 Functional Description Fig.4 shows the global block diagram of the MTC20455. The functions can be grouped into the following: DMT modems Quad or single AFE interface Utopia interface Controller interface Miscellaneous DMT Modem Description The following section essentially describes the sequence of actions for the receive direction, corresponding functions for the transmit direction are readily derived. DSP Front-End The DSP Front-End contains 4 parts in the receive direction: the Input Selector, the Analog Front-End Interface, the Decimator and the Time Equaliser. The input selector is used internally to enable test loopbacks inside the chip. The Analog Front-End Interface transfers 1 6-bits word, multiplexed on 4 input/ output signals. As a result, 4 clock cycles are needed to transfer 1 word. The Decimator receives the 16bits samples at 8.8 MHz (as sent by the Analog Front-End chip) and reduces this rate to 2.2 MHz. The Time Equaliser (TEQ) module is an FIR filter with programmable coefficients. Its main purpose is to reduce the effect of Inter-Symbol Interference (ISI) by shortening the channel impulse response. Both the Decimator and TEQ can be bypassed. In the transmit direction, the DSP Front-End includes: sidelobe filtering, clipping, delay equalisation and interpolation. The sidelobe filtering and delay equalisation are implemented by IIR filters, reducing the effect of echo in FDM systems. Clipping is a statistical process limiting the amplitude of the output signal, optimising the dynamic range of the AFE. The interpolator receives data at 2.2 MHz and generates samples at a rate of 8.8 MHz. Figure 4. DSP Front-End Bypass Analog Interface IN select AFE I/F DEC TEQ To DMT modem DMT Modem This computational module is a programmable DSP unit. Its instruction set enables functions like FFT, IFFT, Scaling, Rotor and Frequency Equali-sation (FEQ). This block implements the core of the DMT algorithm as specified in ANSI T1.413. In the RX path, the 512-point FFT transforms the time-domain DMT symbol into a frequency domain representation which can be further decoded by the subsequent de-mapping stages. After the first stage time / domain equalisation and FFT block - an essentially ICI (InterCarrier Interference) - free carrier information stream has been obtained. This stream is still affected by carrier-specific channel distortion resulting in an attenuation of the signal 12/23 MTC20455 amplitude and a rotation of the signal phase. To compensate for these effects, the FFT is followed by a Frequency domain equaliser (FEQ) and a Rotor (phase shifter). In the TX path, the IFFT transforms the DMT symbol generated in the frequency domain by the mapper into a time domain representation. The IFFT block is preceded by a Fine Tune Gain and a Rotor stage, allowing for a compensation of the possible frequency mismatch between the master clock frequency and the transmitter clock frequency (which may be locked to another reference). The FFT module is a slave DSP engine controlled by the transceiver controller. It works off line and communicates with the other blocks via buffers controlled by the DSTU (DMT Symbol Timing Unit)block. The DSP executes a program stored in a RAM area, a very flexible implementation open for future enhancements. Figure 5. DMT Modem Trellis coding From DSP PE FFT FEQ Rotor Demapper FEQ Coefficients FEQ Update Monitor Monitor Indications DPLL The Digital PLL module receives a metric for the phase error of the pilot tone. In general, the clock frequencies at the transmitter and receiver do not match exactly. The phase error is filtered and integrated by a low pass filter, yielding an estimation of the frequency offset. Various processes can use this estimate to deal with the frequency mismatch. In particular, small accumulated phase errors can be compensated in the frequency domain by a rotation of the received code constellation (Rotor). Larger errors are compensated in the time domain by inserting or deleting clock cycles in the sample input sequence. Mapper/Demapper, Monitor, Trellis Coding, FEQ Update The Demapper converts the constellation points computed by the FFT to a block of bits. This essentially consists in identifying a point in a 2D QAM constellation plane. The Demapper supports trellis coded demodulation and provides a Viterbi maximum likelihood estimator. When the trellis is active, the Demapper receives an indication for the most likely constellation subset to be used. In the transmit direction, the Mapper performs the inverse operation, mapping a block of bits into one constellation point (in a complex x+jy representation) which is passed to the IFFT block. The Trellis Encoder generates redundant bits to improve the robustness of the transmission, using a 4-Dimensional Trellis Coded Modulation scheme. The Monitor computes error parameters for carriers specified in the Demapper process. Those parameters can be used for updates of adaptive filters coefficients, clock phase adjustments, error detection, etc. A series of values is constantly monitored, such as signal power, pilot phase deviations, symbol erasures generation, loss of frame, etc. 13/23 MTC20455 Generic TC Layer Functions These functions relate to byte oriented data streams. They are completely described in ANSI T1.413. Additions described in the Issue 2 of this specification are also supported. The data received from the demapper is split into two paths, one dedicated to an interleaved data flow, the other one for a non-interleaved data flow. These data flows are also referred to as slow and fast data flows. The interleaving/-de-interleaving is used to increase the error correcting capabilityof block codes for error bursts. After de-interleaving (if applicable), the data flow enters a Reed-Solomon error correcting code decoder, able to correct a number of bytes containing bit errors. The decoder also uses the information of previous receiving stages that may have detected the errored bytes and have labelled them with an "erasure" indication. Each time the RS decoder detects and corrects errors in a RS codeword, an RS correction event is generated. The occurrence of such events can be signalled to the management layer. After leaving the RS decoder, the corrected byte stream is descrambled in the PMD (Physical Medium Dependent) descramblers. Two descramblers are used, for interleaved and non-interleaved data flows. These are defined in ANSI T1.413. After descrambling, the data flows enter the Deframer that extracts and processes bytes to support physical layer-related functions according to ANSI T1.413. The ADSL frames indeed contain physical layer-related information in addition to the data passed to the higher layers. In particular, the deframer extracts the EOC (Embedded Operations Channel), the AOC (ADSL Overhead Control) and the indicators bits and passes them to the appropriate processing unit (e.g. the transceiver controller). The deframer also performs a CRC check (Cyclic Redundancy Check) on the received frame and generates events in case of error detection. Event counters can be read by management processes. The outputs of the deframer are an interleaved and a fast data stream. These data streams can either carry ATM cells or another type of traffic. In the latter case, the ATM specific TC layer functional block, described hereafter, is bypassed and the data stream is directly presented at the input of the interface module. Figure 6. Generic TC Layer Functions AST Indications bits AOC EOC F RS coding PMD descrambler Detramer I PMD descrambler FAST From Demapper De-interleaver To ATM TC ATM Specific TC Layer Functions The 2 byte streams (fast and slow) are received from the byte-based processing unit. When ATM cells are transported, this block provides basic cell functions such as cell synchronisa-tion, cell payload descrambling, idle/-unassigned cell filter, cell Header Error Correction (HEC) and detection. The cell processing happens according to ITU-T I.163 standard. Provision is also made for BER measurements at this ATM cell level. When non cell oriented byte streams are transported, the cell processing unit is not active. 14/23 MTC20455 Figure 7. ATM Specific TC Layer Functions BER FAST Cell Descrambler Synchronizer From Generic TC Cell Descrambler Synchronizer SLOW BER HEC Cell filter HEC Cell filter To Interface Module DMT Symbol Timing Unit (DSTU) The DSTU interfaces with various modules, like DSP Front-End, FFT/IFFT, Mapper/Demapper, RS, Monitor and Transceiver Controller. It consists of a real time and a scheduler module. The real time unit generates a time-base for the DMT symbols (sample counter), superframes (symbol counter) and hyperframes (sync counter). The timebases can be modified by various control features. They are continuously fine-tuned by the DPLL module. The DSTU schedulers execute a program, controlled by program opcodes and a set of variables, the most important of which are real time counters. The transmit and receive sequencers are completely independent and run different programs. An independent set of variables is assigned to each of them. The sequencer programs can be updated in real time. Interface Module The interface module collects cells (from the cell-based function module) or a byte stream (from the deframer). Cells are stored in FIFO's (424 bytes or 8 cells wide, transmit buffers have the same size), from which they are extracted by the interface submodule, providing an Utopia level 2 interface. Analog Front-End Control Interface The Analog Front-End Interface is designed to be connected to the MTC20154 or MTC20454 Analog Front-End component Transmit Interface The 16 bit words are multiplexed on 4 AFTXD output signals. As a result 4 cycles are needed to transfer 1 word. Refer to Table 10 for the bit/pin allocation for the 4 cycles. The first of 4 cycles is identified by the CLWD signal (Fig.7). The Analog Front-End fetches the 16 bit word to be multiplexed on AFTXD from the Tx Digital Front-End module. Table 10. Bits assigned to pins/time slot for single line interface Cycle 0 AFRXD_i[0] AFRXD_i[1] AFRXD_i[2] AFRXD_i[3] GP_IN b0 b1 b2 b3 t0 Cycle 1 b4 b5 b6 b7 t1 Cycle 2 b8 b9 b10 b11 t2 Cycle 3 b12 b13 b14 b15 t3 15/23 MTC20455 Table 11. Bits assigned to pins/time slot for muxed-line interface Cycles AFRXD_1[0] AFRXD_1[1] AFRXD_1[2] AFRXD_1[3] 0 b0 b1 b2 b3 1 b4 b5 b6 b7 2 b0 b1 b2 b3 3 b4 b5 b6 b7 4 b0 b1 b2 b3 5 b4 b5 b6 b7 6 B0 b1 b2 b3 7 b4 b5 b6 b7 8 b8 b9 b10 b11 9 b12 b13 b14 b15 10 b8 b9 b10 b11 11 b12 b13 b14 b15 12 b8 b9 b10 b11 13 b12 b13 b14 b15 14 b8 b9 b10 b11 15 b12 b13 b14 b15 line 0 line 1 line 2 line 3 line 0 line 1 line 2 line 3 Receive Interface The 16 bit receive word is multiplexed on 4 AFRXD input signals. As a result 4 cycles are needed to transfer 1 word. Refer to Table 11 for the bit/pin allocation for the 4 cycles. The first of 4 cycles is identified by the CLWD signal. (Fig.9). The CLWD must repeat after 4 MCLK cycles. Figure 8. Receive word timing diagram for single line Interface MCLK_i CLWD_i AFRXD_i Cycle0 GP_IN test0 test1 test test3 Cycle1 Cycle2 Cycle3 Figure 9. Receive word timing diagram for muxed line interface MCLK_1 CLWD_1 AFRXD_1 Cycle 0 1 2 3 line 1 4 5 6 7 8 9 line 0 10 1 12 11 13 14 15 line 0 line 2 line 3 line 1 line 2 line 3 Table 12. Transmitted bits assigned to signal/time slot for single-line interface Cycle 0 AFTXD_I[0] AFTXD_I[1] AFTXD_I[2] AFTXD_I[3] POWER_DOWN_i b0 b1 b2 b3 t0 Cycle 1 b4 b5 b6 b7 t1 Cycle 2 b8 b9 b10 b11 t2 Cycle 3 b12 b13 b14 b15 t3 16/23 MTC20455 Table 13. Transmitted bits assigned to signal/time slot for muxed-line interface Cycles AFTXD_1[0] AFTXD_1[1] AFTXD_1[2] AFTXD_1[3] AFTXD_2[0] AFTXD_2[1] AFTXD_2[2] AFTXD_2[3] 0 line 0 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b0 b1 b2 b3 b4 b5 b6 b7 1 2 line 1 b8 b9 b10 b11 b12 b13 b14 b15 b0 b1 b2 b3 b4 b5 b6 b7 3 4 line 2 b8 b9 b10 b11 b12 b13 b14 b15 b0 b1 b2 b3 b4 b5 b6 b7 5 6 line 3 b8 b9 b10 b11 b12 b13 b14 b15 7 Table 14. MCLK, AC Electrical Characteristics AC Electrical Characteristics for MCLK_i Symbol F Tper Th Parameter Clock Frequency Clock Period Clock duty cycle 40 Test Conditions Min Typ 35.328 28.3 60 Max Unit MHz ns % Table 15. AFTXD AC Electrical Characteristics AC Electrical Characteristics for AFTXD_i Symbol Tva Tha Parameter Data valid time Data hold time Test Conditions 20 pF load 20 pF load 4 Min Typ Max 16 Unit ns ns Table 16. CTRLDATA AC Electrical Characteristics AC Electrical Characteristics for CTRLDATA_i Symbol Tvb Thb Parameter Data valid time Data hold time Test Conditions 20 pF load 20 pF load 4 Min Typ Max 20 Unit ns ns Figure 10. Analog front end receive interface timing diagram MCLK_i Ts Th AFRXD_i CLWD_i 17/23 MTC20455 Table 17. AFRXD AC Electrical Characteristics AC Electrical Characteristics for AFRXD Symbol Ts Th Parameter Data setup time Data setup time Test Conditions Min 5 1 Typ Max Unit ns ns Digital Interface With a Utopia Level 2 Interface the ATM forum takes the ATM layer chip as a reference. It defines the direction from ATM to physical layer as the Transmit direction. The direction from physical layer to ATM direction is referred to as the receive direction. Fig.9 shows the interconnection between ATM and PHY layer devices. Tx reference and Rx reference are supported for network timing. The UTOPIA interface transfers one byte in a single clock cycle, as a result cells are transferred in 53 clock cycles. Both transmit and receive interfaces are synchronised on clocks generated by the ATM layer chip, and as no specific relationship between Receive and Transmit clock is assumed, they must be regarded as mutually asynchronous clocks. Flow control signals are available to match the bandwidth constraints of the physical layer and the ATM layer. The UTOPIA level 2 supports point to multi-point configurations by introducing an addressing capability and by making a distinction between polling and selecting a device: - the ATM chip polls a specific physical layer chip by putting its address on the address bus when the enable (notTxEnb/notRxEnb) line is asserted. The addressed physical layer answers the next cycle via a cell available line (TxClav/RxClav) reflecting its status at that time. - the ATM chip selects a specific physical layer chip by putting its address on the address bus when the enable line is deasserted and asserting the enable line on the next cycle. The addressed physical layer chip will be the target or source of the next cell transfer. Figure 11. Signals at Utopia Level 2 Interface PH Y RxAddr 1 PHY Receive RxClav ATM Receive 5 A TM notRxEnb RxClk 8 RxData RxSOC TxAddr 1 PHY Transmit TxClav 5 notTxEnb TxClk TxData TxSOC 8 ATM Transmit 18/23 MTC20455 Utopia Level 2 Signals The physical layer chip sends cell data towards the ATM layer chip. The ATM layer chip polls the status of the FIFO of the physical layer chip. Refer to Table 6 for a list of interface signals. The cell exchange proceeds like: a) The physical layer chip signals the availability of a cell by asserting RxClav when polled by the ATM chip. b) The ATM chips selects a physical layer chip, then starts the transfer by asserting notRxEnb. c) If the physical layer chip has data to send, it puts them on the RxData line the cycle after it sampled notRxEnb active. It also advances the offset in the cell. If the data transferred is the first byte of a cell, RxSOC is 1b at the time of the data transfer, 0b otherwise. d) The ATM chip accepts the data when they are available. If RxSOC was 1b during the transfer, it resets its internal offset pointer to the value 1, otherwise it advances the offset in the cell. MTC20455 Utopia Level 2 MPHY Operation Utopia level 2 MPHY operation can be done by various interface schemes. The MTC20455 supports only the required mode, this mode is referred to as operation with 1 TxClav and 1 RxClav. PHY Device Identification The MTC20455 holds 2 PHY layer Utopia ports, one is dedicated to the fast data channel, the other one to the interleaved data channel. The associated PHY address is specified by the PHY_ADDR_x fields the Utopia PHY address register. Beware that an incorrect address configuration may lead to bus conflicts. MTC20136 Transceiver Controller Interface Table 18. All signals Symbol tr, tf Ci Co Input load Output load Parameter Rise and Fall time (10% - 90%) Min Typ Max 3 10 20 Unit ns pF pF Figure 12. PCLK Clock frequency Symbol f Parameter PCLK clock frequency Min 8 Typ Max 33 Unit MHz Table 19. Address with respect to ALE Symbol tr,tf Talew Tavs Tavh Parameter Rise and Fall time (10% - 90%) ALE pulse width Address valid setup time Address valid hold time 12 7 8 Min Typ Max 4 Unit ns ns ns ns 19/23 MTC20455 Figure 13. Address and ALE timing diagram Talew ALE Tavs AD [15:0] Tavh Table 20. Data input with respect to clock Symbol Tdh Tds Data write hold time Data write setup time Parameter Min 3 10 Max Unit ns ns Table 21. Data output with respect to clock Symbol Tzd Tdz Parameter Data active delay from clock, Z to data Data inactive delay from clock, data to Z Min 3 3 Max 20 20 Unit ns ns Table 22. WR_RDB input specification with respect to PCLK Symbol Twrs Twrh Parameter setup WR_RDB to clock hold WR_RDB to clock Min 10 3 Max Unit ns ns Table 23. CSB input specification with respect to PCLK Symbol Twrs Twrh setup CSB to clock hold CSB to clock Parameter Min 10 3 Max Unit ns ns Table 24. RDYB output with respect to PCLK Symbol Tzrd Trdz Parameter RDYB active delay from clock, Z to 0 RDYB inactive delay from clock, 0 to Z Min 3 3 Max 19 19 Unit ns ns 20/23 MTC20455 DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.65 30.95 27.90 0.25 3.17 0.22 0.13 30.95 27.90 mm TYP. MAX. 4.07 0.010 3.42 3.67 0.38 0.23 31.20 28.00 25.35 0.65 31.20 28.00 25.35 0.80 1.60 0(min.), 7(max.) 0.95 0.026 31.45 28.10 1.219 1.098 31.45 28.10 0.125 0.009 0.005 1.219 1.098 MIN. inch TYP. MAX. 0.160 OUTLINE AND MECHANICAL DATA 0.135 0.144 0.015 0.009 1.228 1.102 0.998 0.026 1.228 1.102 0.998 0.031 0.063 1.238 1.106 1.238 1.106 0.037 PQFP160 21/23 MTC20455 mm DIM. MIN. A A1 A2 b D D1 E E1 e f ddd 0.720 0.650 11.85 0.450 11.85 1.210 0.270 1.120 0.500 12.00 10.40 12.00 10.40 0.800 0.800 0.880 0.950 0.120 0.028 0.025 12.15 0.466 0.550 12.15 0.018 0.466 TYP. MAX. 1.700 MIN. 0.047 0.010 inch TYP. MAX. 0.067 OUTLINE AND MECHANICAL DATA 0.044 0.02 0.472 0.409 0.472 0.409 0.031 0.031 0.034 0.037 0.004 0.478 0.021 0.478 Body: 12 x 12 x 1.7mm LFBGA160 Low Profile Fine Pitch Ball Grid Array 7254214 A 22/23 MTC20455 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com 23/23 |
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